1) Field of the Invention
The present invention relates to an amplifier and a semiconductor storage device, which includes an amplifier, such as a nonvolatile memory which has a storage data reading circuit and is electrically writable, i.e., an erasable programmable read-only memory (hereinafter referred to as an EPROM).
2) Description of the Related Art
Conventional art in the technology concerning the EPROM is disclosed, for example, in Japanese Patent Kokai No. 2000-331486. The EPROM includes a plurality of memory cell blocks which are selected by block selection signals. The memory cell blocks are arranged in parallel with each other and each of the memory cell blocks includes a plurality of word lines decoded by external address inputs, a plurality of first bit lines arranged in parallel with each other having predetermined spaces therebetween so as to be directed perpendicular to the word lines, and a plurality of second bit lines respectively arranged beside the first bit lines so as to be parallel with each other. The second bit lines are connected to grounding potential nodes (hereinafter referred to as a GND) in response to signals decoded by the address input. Memory cells each including a MOS transistor are respectively positioned at intersecting points of the word lines, and the first and second bit line pairs so as to form a matrix pattern. Each memory cell includes a source, a drain and a floating gate, which are respectively connected to the first bit line, the second bit line and the word line.
Around the memory cell blocks, there are provided circuits such as writing circuits for writing data and reading circuits for reading data. These circuits are connected to the memory cell blocks. The writing circuit writes the data to the memory cell in, for example, the following procedures: after data in all of the memory cells are erased, a memory cell is selected by the word line, and a negative high voltage is applied between the source and the drain of the selected memory cell so as to charge electrons to the floating gate. Accordingly, data ‘0’ is written to the memory cell. The memory cell having the data ‘0’ maintains the electron-charged state in the floating gate, even if the power supply is stopped, until the data is erased by an ultraviolet ray or an X-ray. On the other hand, a memory cell in which data is not written is in a data ‘1’ state.
The reading circuit reads the data in, for example, the following procedures: the first bit line is set at a high level (hereinafter referred to as an ‘H’ level) and the second bit line is set at a low level, i.e., a grounding potential level (hereinafter referred to as an ‘L’ level), and then the external address input is decoded so as to select the word line. With respect to the memory cell having the data ‘0’, even though an electrical potential difference is generated between the source of the first bit line and the drain of the second bit line upon selection of the word line connected to the floating gate, no channel is formed within the memory cell, and no current flows between the source and the drain. Accordingly, an electrical potential of the first bit line is kept at the ‘H’ level, and the electrical potential is inverted and amplified by the reading circuit so that data ‘0’ having the grounding potential is output. On the contrary, with respect to the memory cell having the data ‘1’, when an electrical potential difference is generated between the source of the first bit line and the drain of the second bit line upon selection of the word line connected to the floating gate during a reading operation, a channel is formed within the memory cell, and thus an electrical current flows between the source of the first bit line and the drain of the second bit line. Accordingly, an electrical potential of the first bit line is reduced to the electrical potential of the grounding potential side having the ‘L’ level, and the electrical potential of the first bit line is inverted and amplified by the reading circuit so that data ‘1’ having the power supply potential (hereinafter referred to as a VCC) is output.
The conventional EPROM disclosed in Japanese Patent Kokai No. 2000-331486 however has the following problem.
Because of a capacity increase of the semiconductor storage device in recent years, the number of word lines as well as the number of first and second bit lines of memory cell blocks are increasing. In addition, lengths of the lines are increasing. Furthermore, the increase of lengths of the first and second bit lines increases an inter-wire capacitance, i.e., a parasitic capacitance, between the first bit line and the second bit line which are adjacent to each other.
Suppose, for example, that a reading operation from the ‘1’ memory cell is shifted to a reading operation from the ‘0’ memory cell. An electrical current initially flows from the source on the first bit line side having the ‘H’ level to the drain on the second bit line side having the grounding potential level in the ‘1’ memory cell. When the above reading operation from the ‘1’ memory cell is shifted to the reading operation from the ‘1’ memory cell, the electrical potential of the first bit line at the source side tends to increase toward the ‘H’ level, since no electrical current flows in the ‘0’ memory cell. However, since the parasitic capacitance exists between the first bit line and the second bit line, an electrical current momently flows through the parasitic capacitance by a coupling effect of the parasitic capacitance, and the electrical potential of the first bit line is reduced to the grounding potential side. Subsequently, the parasitic capacitance is charged and the electrical current stops flowing so that the first bit line increases to the ‘H’ level. The momently decrease of the first bit line by the coupling effect affects the reading circuit and finally causes the problem of a reading access delay of a short period Δt at the read output.
As described above, because of the remarkably increasing value of the parasitic capacitance between the first bit line and the second bit line in recent years, the reading access delay in proportional to the parasitic capacitance appears to be an unignorable problem. Therefore, it is expected to solve the problem without using a complex circuit structure.